Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Many modern computing systems utilize multi-core processors having two or more cores interfaced for enhanced performance and efficient processing of multiple tasks and threads. Data used in execution of single and multiple thread applications may be stored across multi-level caches of the cores of the multi-core processors. During operation, such data may be accessed from the cached locations.
During operation, a memory reference such as for a LOAD or a STORE instruction, may be looked-up in a primary cache such as a level one (L1) cache of the computing system. Additionally, the memory reference may also be looked-up in a secondary cache such as a level two (L2) cache, for example when there is a cache miss in the primary cache. Such cache look-ups in multi-core processors can consume a significant amount of power.
Further, access latency to lower level caches of the cache hierarchy in multi-level caches can affect performance of the multi-level cache systems. For example, on-chip interconnect latency of multi-level caches may increase as the number of cores increase in such systems and may lead to increase in overall energy consumption.